1. Field of the Invention
The present disclosure relates generally to a semiconductor fabrication and, more particularly, to a method for forming dual gate electrodes using a damascene gate process.
2. Background of the Related Art
Threshold voltage deviation in sub-100 nm MOSFETs is a serious problem whose origins are considered to be the fluctuation of gate length, channel impurity density, work function of gate material, interface trap density, fixed charge density in gate oxide and gate oxide thickness, etc. The interface traps and the fixed charge are created during the plasma process such as RIE and ion implantation process. By fabricating gate electrodes after a source and drain region formation, plasma and thermal damage on the gate electrodes can be reduced. This is called the damascene gate process.
FIG. 1 is a cross-sectional view illustrating dual gate electrodes in accordance with a prior art. Steps for fabricating the dual gate electrodes shown in FIG. 1 are as follows. First, an STI (Shallow Trench Isolation) structure 150 is formed in a substrate 100. An N-well and a P-well are respectively formed in the substrate 100 by ion implantation processes. Subsequently, a thick gate oxide layer 180 and a thin gate oxide layer 190 are respectively formed on the substrate 100. An annealing process is then performed for the resulting structure under a N2 atmosphere. In this step, the thin gate oxide layer 190 is relatively highly nitrided compared to the thick gate oxide layer 180, resulting in the deterioration of the characteristic of a semiconductor device.
Subsequently, dummy polysilicon is deposited on the entire surface of the substrate 100. After a photoresist pattern is formed on the dummy polysilicon by a common photolithography process, dummy gates are formed by an etching process. Subsequently, LDD structures 130 are respectively formed around each of the dummy gates by implanting low concentration ions. Spacers 160 made of nitride are then formed on the lateral faces of each of the dummy gates. Source and drain regions 140 with the LDD structures 130 are then respectively formed around the each of the dummy gates by implanting high concentration ions. Subsequently, a predetermined thermal treatment is performed to activate the ions in the source and drain regions 140 having the LDD structures 130. After the dummy gates are removed, another polysilicon 120 is deposited where the dummy gates are removed. A liner layer is formed on the each of the gate electrode. A CMP process is then performed to planarize the surface of the resulting structure. Subsequently, a silicide layer 170 is formed on the source and drain regions 140 with the LDD structures 130 and the top of polysilicon 120 of the gate electrodes. Dual gate electrodes are then completed.
Korean Patent Publication No. 2003-0,061,791 discloses the structure and fabrication process of a completely planar, damascene double gated transistor. The structure has a novel self-aligned, hyper-abrupt retrograde body and a zero-parasitic, endwall gate-body connection. The structure also provides for increased density and enables ultra low power to be utilized. The methods also provide for simultaneously making both four-terminal and dynamic threshold MOSFET devices.
However, conventional methods have several shortcomings as follows. First, the thin gate oxide layer may be easily contaminated by nitride impurities which are used in the annealing process for the thick gate oxide layer. Second, a stable thermal budget may be difficult to achieve because the gate oxide layer does not have a high dielectric constant.